Enhance implementation of embedded concurrent DES functional units using spatial parallelism approach on FGPA for better throughput - Rana Khazaal Khudhair (School of Computer and Communication Engineering, Universiti Malaysia Perlis, 2015)
In the present work, DES algorithm implementation optimization has been achieved through the DES unit components replication to four concurrent DES functional units. This operation has been performed by using a spatial parallelism approach. The input/output data has been stored in the separated RAMs which it is dual port memories that supports the read and write processes concurrently. This approach is speedup the processing of data. Furthermore, the frequency which is supported by the board has been duplicated from 50 up to 200 MHz by utilizing the Phase Locked Loop (PLL) to avoid any delay of DES functional unit implementation. All of this has led to enhance and speedup the implementation of DES algorithm and increase throughput as well. The design and implementation is performed on Altera Nios II Embedded Evaluation Kit (NEEK) board.