Design and analysis of floting point multiplier
This final year project is about to design a 32-bits floating-point Multiplier, calculate the speed, delay, power delay product and area (in layout's size) for design, and to perform analysis on the experimental results in terms of the total power consumption, speed, delay, power delay product...
保存先:
| 第一著者: | |
|---|---|
| フォーマット: | 電子媒体 ソフトウェア データベース |
| 言語: | English |
| 主題: | |
| タグ: |
タグ追加
タグなし, このレコードへの初めてのタグを付けませんか!
|
| 要約: | This final year project is about to design a 32-bits floating-point Multiplier, calculate the speed, delay, power delay product and area (in layout's size) for design, and to perform analysis on the experimental results in terms of the total power consumption, speed, delay, power delay product and area. |
|---|---|
| 記述事項: | Final Year Project |
| 物理的記述: | 1 CD-ROM 4 3/4 in. |