Design and analysis of floting point multiplier

Design and analysis of floting point multiplier

This final year project is about to design a 32-bits floating-point Multiplier, calculate the speed, delay, power delay product and area (in layout's size) for design, and to perform analysis on the experimental results in terms of the total power consumption, speed, delay, power delay product...

Disgrifiad llawn

Wedi'i Gadw mewn:

Manylion Llyfryddiaeth
Prif Awdur:	Zariah Asari (Awdur)
Fformat:	Electronig Meddalwedd Cronfa ddata
Iaith:	English
Pynciau:	Microelectronics.
Tagiau:	Ychwanegu Tag Dim Tagiau, Byddwch y cyntaf i dagio'r cofnod hwn!

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