Design and analysis of floting point multiplier
This final year project is about to design a 32-bits floating-point Multiplier, calculate the speed, delay, power delay product and area (in layout's size) for design, and to perform analysis on the experimental results in terms of the total power consumption, speed, delay, power delay product...
Saved in:
| 主要作者: | |
|---|---|
| 格式: | 電子 軟件 Database |
| 語言: | English |
| 主題: | |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|