Design and analysis of floting point multiplier
This final year project is about to design a 32-bits floating-point Multiplier, calculate the speed, delay, power delay product and area (in layout's size) for design, and to perform analysis on the experimental results in terms of the total power consumption, speed, delay, power delay product...
Saved in:
主要作者: | Zariah Asari (Author) |
---|---|
格式: | 电子 软件 数据库 |
语言: | English |
主题: | |
标签: |
添加标签
没有标签, 成为第一个标记此记录!
|
相似书籍
-
Design and analysis of floating point divider
由: Siti Aminah Hussen -
Analysis & design low power multiplier using TSMC 0.18um CMOS technology /
由: Norsaifulrudin Mat Zuki
出版: (2008) -
Design and realization of high speed multiplier accumulator (MAC) unit for low power applications
由: Mohd Nazri Mad Rejab -
High speed 8-Bits X 8-Bits wallace tree multiplier
由: Tajul Hamimi Harun -
8-bits X 8-bits modified booth 1's complement multiplier
由: Norafiza Salehan