16-bits carry look-ahead adder as a high speed adder
This paper put emphasis on designing a modified carry look-ahead adder (CLA) to acquire a high speed carry look ahead in seeing as speed is the significant characteristics to a Central Processor Unit. After some historical background on this emphasize, it was found that there are several ways to in...
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| Autor Principal: | |
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| Formato: | Electrónico Software Base de Datos |
| Idioma: | English |
| Subjects: | |
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| Summary: | This paper put emphasis on designing a modified carry look-ahead adder (CLA) to acquire a high speed carry look ahead in seeing as speed is the significant characteristics to a Central Processor Unit. After some historical background on this emphasize, it was found that there are several ways to increase the speed of a CLA. In this project, pipelining techniques has been carrying out. It reduces delay by multiple are overlap in execution. This project simulated its output using Quartus II software and Altera UP2 board implementation to present the speed performance of the design architectures. |
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| descrición da copia: | Final year Project |
| Descrición Física: | 1 CD-ROM 4 3/4 in. |