High speed six operands 16-bits carry save adder
The purpose of the project is to implement a high-speed three levels six operands of 16-bits CSA with RCA at the end of the design. The objective of this project are design faster execution of CSA using gate logic design and implement it to the Altera UP2 board. The project is simulated and clarifie...
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| Format: | Electronic Software Database |
| Language: | English |
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| Summary: | The purpose of the project is to implement a high-speed three levels six operands of 16-bits CSA with RCA at the end of the design. The objective of this project are design faster execution of CSA using gate logic design and implement it to the Altera UP2 board. The project is simulated and clarifies the output using Quartus II software and Altera UP2 board implementation to verify the design architectures. The high-speed circuit was designed by using smallest delay between five different logic gates Full Adder (FA) and by adding pipeline. This project has been achieved from 16.84MHz to the 90.09MHz speed on EPF10K70RC240-4 device. This result contribute CSA is in faster speed. |
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| Item Description: | Final Year Project |
| Physical Description: | 1 CD-ROM 4 3/4 in. |