Design and realization of high speed multiplier accumulator (MAC) unit for low power applications
In this final year project, the designed multiplier accumulator (MAC) unit is an eight bit MAC unit in which capable to multiply unsigned and signed number. The methodologies need to carry out this project is to use the Mentor Graphic tools to draw and design whole MAC unit.
Sábháilte in:
Príomhchruthaitheoir: | Mohd Nazri Mad Rejab (Údar) |
---|---|
Formáid: | Leictreonach Bogearraí Bunachar sonraí |
Teanga: | English |
Ábhair: | |
Clibeanna: |
Cuir clib leis
Níl clibeanna ann, Bí ar an gcéad duine le clib a chur leis an taifead seo!
|
Míreanna comhchosúla
-
Low power multiplier accumulator (MAC) unit using multiple threshold CMOS
de réir: Thin, Tan Fhan -
Low power multiplier accumulator (MAC) unit using sleepy stack technique
de réir: Aaron Selvam Thangamany -
High speed 8-Bits X 8-Bits wallace tree multiplier
de réir: Tajul Hamimi Harun -
Analysis & design low power multiplier using TSMC 0.18um CMOS technology /
de réir: Norsaifulrudin Mat Zuki
Foilsithe / Cruthaithe: (2008) -
Design and analysis of floting point multiplier
de réir: Zariah Asari