Design and realization of high speed multiplier accumulator (MAC) unit for low power applications
In this final year project, the designed multiplier accumulator (MAC) unit is an eight bit MAC unit in which capable to multiply unsigned and signed number. The methodologies need to carry out this project is to use the Mentor Graphic tools to draw and design whole MAC unit.
Сохранить в:
Главный автор: | Mohd Nazri Mad Rejab (Автор) |
---|---|
Формат: | Электронный ресурс Программное обеспечение База данных |
Язык: | English |
Предметы: | |
Метки: |
Добавить метку
Нет меток, Требуется 1-ая метка записи!
|
Схожие документы
-
Low power multiplier accumulator (MAC) unit using multiple threshold CMOS
по: Thin, Tan Fhan -
Low power multiplier accumulator (MAC) unit using sleepy stack technique
по: Aaron Selvam Thangamany -
High speed 8-Bits X 8-Bits wallace tree multiplier
по: Tajul Hamimi Harun -
Analysis & design low power multiplier using TSMC 0.18um CMOS technology /
по: Norsaifulrudin Mat Zuki
Опубликовано: (2008) -
Design and analysis of floting point multiplier
по: Zariah Asari