Design and realization of high speed multiplier accumulator (MAC) unit for low power applications
In this final year project, the designed multiplier accumulator (MAC) unit is an eight bit MAC unit in which capable to multiply unsigned and signed number. The methodologies need to carry out this project is to use the Mentor Graphic tools to draw and design whole MAC unit.
Shranjeno v:
Glavni avtor: | Mohd Nazri Mad Rejab (Author) |
---|---|
Format: | Elektronski Software Database |
Jezik: | English |
Teme: | |
Oznake: |
Označite
Brez oznak, prvi označite!
|
Podobne knjige/članki
-
Low power multiplier accumulator (MAC) unit using multiple threshold CMOS
od: Thin, Tan Fhan -
Low power multiplier accumulator (MAC) unit using sleepy stack technique
od: Aaron Selvam Thangamany -
High speed 8-Bits X 8-Bits wallace tree multiplier
od: Tajul Hamimi Harun -
Analysis & design low power multiplier using TSMC 0.18um CMOS technology /
od: Norsaifulrudin Mat Zuki
Izdano: (2008) -
Design and analysis of floting point multiplier
od: Zariah Asari