Low power multiplier accumulator (MAC) unit using sleepy stack technique
The main objective of this final year project is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. In this final year project, a novel circuit structure called "sleepy stack" is presented. The sleepy stack is a combination of two well known low-leakage t...
Сохранить в:
Главный автор: | Aaron Selvam Thangamany (Автор) |
---|---|
Формат: | Электронный ресурс Программное обеспечение База данных |
Язык: | English |
Предметы: | |
Метки: |
Добавить метку
Нет меток, Требуется 1-ая метка записи!
|
Схожие документы
-
Low power multiplier accumulator (MAC) unit using multiple threshold CMOS
по: Thin, Tan Fhan -
Design and realization of high speed multiplier accumulator (MAC) unit for low power applications
по: Mohd Nazri Mad Rejab -
Design and analysis of low power ALU unit, program counter and instruction register using sleepy stack technique
по: Wan Nurul Liyana Wan Zulkefle -
Analysis & design low power multiplier using TSMC 0.18um CMOS technology /
по: Norsaifulrudin Mat Zuki
Опубликовано: (2008) -
Design and analysis of floting point multiplier
по: Zariah Asari