Low power multiplier accumulator (MAC) unit using sleepy stack technique
The main objective of this final year project is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. In this final year project, a novel circuit structure called "sleepy stack" is presented. The sleepy stack is a combination of two well known low-leakage t...
Na minha lista:
Autor principal: | Aaron Selvam Thangamany (Author) |
---|---|
Formato: | Recurso Electrónico Software Base de Dados |
Idioma: | English |
Assuntos: | |
Tags: |
Adicionar Tag
Sem tags, seja o primeiro a adicionar uma tag!
|
Registos relacionados
-
Low power multiplier accumulator (MAC) unit using multiple threshold CMOS
Por: Thin, Tan Fhan -
Design and realization of high speed multiplier accumulator (MAC) unit for low power applications
Por: Mohd Nazri Mad Rejab -
Design and analysis of low power ALU unit, program counter and instruction register using sleepy stack technique
Por: Wan Nurul Liyana Wan Zulkefle -
Analysis & design low power multiplier using TSMC 0.18um CMOS technology /
Por: Norsaifulrudin Mat Zuki
Publicado em: (2008) -
Design and analysis of floting point multiplier
Por: Zariah Asari