CMOS Inverter-Circuit Characterization and Performance Estimation - Chew, Chee Ting (School of Microelectronic Engineering, University Malaysia Perlis, 2013)
This thesis tries to examine the CMOS inverter for Circuit Characterization and Performance Estimation. This technique is designed using Design Architecture IC (DA/IC) from Mentor Graphic Software. A delay and power model of a CMOS inverter driving a resistive-capacitance load is presented. Although transistors are complicated devices with non-linear current-voltage relationships for the purpose of delay estimation in digital circuits, they can be approximated quite well as having constant capacitance and an effective resistance, R, when ON. Accurate and analytical expression for the output voltage waveform, the propagation delay and the short circuit power dissipation are derived by solving the system of differential equations which describe the behavior of the circuit. The calculated propagation delay and short circuit dissipation are in very good agreement with simulation results. The propagation delay of a gate can be minimized by reduce load capacitance, CL. For this part when tried to put in some capacitance value and found out capacitance smaller the minimal propagation delay time also smaller. Second is increased the W/L ratio of the transistors. This is the most powerful and effective performance optimization tool. Third is increased VDD, the delay of a gate can be modulated by modifying the supply voltage.