Logical Effort of CMOS 4-2 Compressors for Arithmetic Circuits/
The method of Logical Effort on CMOS circuit design for speed, it is implied on a few types topologies of the 4-2 compressor. The delay is calculated with Logical Effort concept, choosing the critical path of each circuit, obtain the stage effort, delay and the transistor size for each 4-2 compresso...
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| Autor principal: | |
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| Formato: | Tese Software livro eletrônico |
| Idioma: | English |
| Publicado em: |
Perlis, Malaysia
School of Microelectronic Engineering, University Malaysia Perlis
2011.
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