Fabrication and characterization of engineered tunnel barrier for nonvolatile memory application /
This study focuses on the Variable Oxide Thickness (VARIOT) approach of engineered tunnel barrier where the asymmetrical VARIOT structure with the effective oxide thickness (EOT) ranging from 6 nm to 14 nm were studied in the form of MOS capacitor structure.
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| Main Author: | |
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| Format: | Thesis Software eBook |
| Language: | English |
| Published: |
Perlis, Malaysia
School of Microelectronic Engineering
2012.
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| 245 | 1 | 0 | |a Fabrication and characterization of engineered tunnel barrier for nonvolatile memory application / |c Zarimawaty Zailan. |
| 264 | 1 | |a Perlis, Malaysia |b School of Microelectronic Engineering |c 2012. | |
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| 502 | |a Thesis (Master of Science)--Universiti Malaysia Perlis. School of Microelectronic Engineering, 2012. | ||
| 504 | |a Includes bibliographical references (pages 98-100). | ||
| 520 | 3 | |a This study focuses on the Variable Oxide Thickness (VARIOT) approach of engineered tunnel barrier where the asymmetrical VARIOT structure with the effective oxide thickness (EOT) ranging from 6 nm to 14 nm were studied in the form of MOS capacitor structure. | |
| 650 | 0 | |a Nonvolatile random-access memory. | |
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