Statistical modelling and optimization of input process parameters variations in silicon-on-insulator MOSFET device - Muhammad Nazirul Ifwat Abd Aziz (2017)
The steady miniaturization of the conventional (planar bulk) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been effective in providing continual improvements in integrated circuit performance. However, increased leakage current and variability in transistor performance are the major challenges for continued scaling of bulk Si MOSFET technology. Therefore, Silicon-on-insulator (SOI) technology has been recognized as an effective approach to mitigate the short-channel effect (SCE) problems. SOI technology allows optimum electrical characteristics to be obtained for low power and high performance circuits. In this research, the impact of the process parameters such as halo implantation energy, halo implantation dose, Source/Drain implantation Dose, and Source/Drain (S/D) implantation energy on the response characteristics for the NMOS and PMOS SOI MOSFET devices were investigated. The virtual fabrication of the device was performed using ANTHENA module while the device electrical characteristics . were simulated using ATLAS module. ANTHENA and ATLAS are the modules contained in Silvaco TCAD software. These two modules were combined with an appropriate statistical method to aid in designing and optimizing the process parameters. In the optimization of the process parameter variations towards the multiple device's characteristics of SOI MOSFET devices, Taguchi method and 2k factorial designs were used. The performance between these two methods in the NMOS and PMOS SOI MOSFET device was evaluated. Based on the observation, it was found that the results given by the Taguchi method were more accurate than 2k Factorial designs due to the presence of noise factors. In PMOS device, the most dominant or .significant factors for SIN Ratio were Halo implantation dose and S/D implantation energy. While the SIN Ratio values after the optimization approach for VTH, SS, IoFF and loN were 91.27dB, -39.37dB, 335.68dB and -80.16dB respectively. Meanwhile, for NMOS, the most dominant or significant factor for SIN Ratio was S/D implantation energy. The SIN ratio values after the optimization approach for VTH, SS, loFF and IoN were 53.64dB, -38.60dB, 234.86dB and 54.70dB respectively . All these values were within the predicted range. In PMOS device, the results showed that the VTH, SS, loFF and IoN after optimization approaches were -0.573V, 92.95mV/dec, 26.04x10- 18A/µm and 98.19µA/µm respectively. For NMOS device, the values of VTH, SS, IoFF and IoN after optimization approaches were +0.546V, 85.08mV/dec, 2.034pA/µm and 344.l 7µA/µm respectively. Most of the results obtained were within the range and met the requirement of low power (LP) technology for the year 2016 as predicted by International Technology Roadmap for Semiconductor (ITRS) 2013. As a conclusion, the design of NMOS and PMOS SOI MOSFET has successfully been created and through the Taguchi method, the optimal solution for the robust design of the devices has successfully been achieved