Implementation of 8x8 bit shift-and-add multiplier using Altera NIOS development board, APEX edition /

Implementation of 8x8 bit shift-and-add multiplier using Altera NIOS development board, APEX edition /

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Bibliographic Details
Main Author: Asrul Nazif Kamaludin (Author)
Corporate Author: Kolej Universiti Teknologi Tun Hussein Onn. Fakulti Kejuruteraan Elektrik dan Elektronik
Format: Thesis Book
Language:English
Published: Batu Pahat : Kolej Universiti Teknologi Tun Hussein Onn, 2006.
Subjects:
Verilog (Computer hardware description language).
Microprocessor.
Electronic digital computers > Design and construction > Data processing.
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Description
Physical Description:xviii, 53 pages : illustrations ; 30 cm.

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