Design and realization of high speed multiplier accumulator (MAC) unit for low power applications
In this final year project, the designed multiplier accumulator (MAC) unit is an eight bit MAC unit in which capable to multiply unsigned and signed number. The methodologies need to carry out this project is to use the Mentor Graphic tools to draw and design whole MAC unit.
Saved in:
主要作者: | Mohd Nazri Mad Rejab (Author) |
---|---|
格式: | 电子 软件 数据库 |
语言: | English |
主题: | |
标签: |
添加标签
没有标签, 成为第一个标记此记录!
|
相似书籍
-
Low power multiplier accumulator (MAC) unit using multiple threshold CMOS
由: Thin, Tan Fhan -
Low power multiplier accumulator (MAC) unit using sleepy stack technique
由: Aaron Selvam Thangamany -
High speed 8-Bits X 8-Bits wallace tree multiplier
由: Tajul Hamimi Harun -
Analysis & design low power multiplier using TSMC 0.18um CMOS technology /
由: Norsaifulrudin Mat Zuki
出版: (2008) -
Design and analysis of floting point multiplier
由: Zariah Asari