Low power multiplier accumulator (MAC) unit using sleepy stack technique
The main objective of this final year project is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. In this final year project, a novel circuit structure called "sleepy stack" is presented. The sleepy stack is a combination of two well known low-leakage t...
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| Autor Principal: | |
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| Formato: | Electrónico Software Base de Datos |
| Idioma: | English |
| Subjects: | |
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| Summary: | The main objective of this final year project is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. In this final year project, a novel circuit structure called "sleepy stack" is presented. The sleepy stack is a combination of two well known low-leakage techniques which are the forced stack technique and the sleep transistor technique. |
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| descrición da copia: | Final Year Project |
| Descrición Física: | 1 CD-ROM 4 3/4 in. |